Integration of Electrografted Layers for the Metallization of Deep Through Silicon Vias
نویسنده
چکیده
After many years as a hypothetical possibility, 3D integrated circuits (3D IC) stacking has emerged as a potential key enabler for maintaining semiconductor performance trends. Implementing 3D, however, will almost certainly require development of through-silicon vias (TSVs), which in the past few years have been elevated by the semiconductor industry to the status of a crucial mainstream technology.
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